[ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification

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文件数目：421个文件
文件大小：3.37 GB
收录时间：2021-11-26
访问次数：8
相关内容：CourseLala Udemy Verilog Fundamentals Digital Design Verification

文件meta

~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.mp4
112.94 MB
~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.mp4
108.76 MB
~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).mp4
103.04 MB
~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.mp4
78 MB
~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).mp4
70 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.mp4
59.38 MB
~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.mp4
50.98 MB
~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).mp4
50.86 MB
~Get Your Files Here !/1. Introduction/2. Course overview.mp4
50.49 MB
~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.mp4
49.89 MB
~Get Your Files Here !/1. Introduction/1. Welcome!.mp4
43.64 MB
~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.mp4
42.07 MB
~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.mp4
39.98 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.mp4
39.8 MB
~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.mp4
39.01 MB
~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.mp4
38.64 MB
~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.mp4
37.72 MB
~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.mp4
37.34 MB
~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.mp4
36.7 MB
~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.mp4
36.23 MB
~Get Your Files Here !/4. Verilog Module/1. Verilog Module - the basics.mp4
34.94 MB
~Get Your Files Here !/5. Verilog Design Styles/15. Action Time - 4bit_full_adder structural.mp4
34.07 MB
~Get Your Files Here !/11. Verilog State Machines/1. Discover Finite State Machines.mp4
33.95 MB
~Get Your Files Here !/8. Verilog Sequential Design/12. Action Time - Shift_Reg_SIPO.mp4
33.59 MB
~Get Your Files Here !/7. Verilog Combinational Design/23. Action Time - HEX 7segment decoder.mp4
32.23 MB
~Get Your Files Here !/8. Verilog Sequential Design/21. Action Time - Modulo_N Counter.mp4
32.11 MB
~Get Your Files Here !/11. Verilog State Machines/5. Action Time - Sequence Detector NON Overlaping.mp4
30.89 MB
~Get Your Files Here !/1. Introduction/4. Understand Abstraction Levels.mp4
30.63 MB
~Get Your Files Here !/8. Verilog Sequential Design/2. Action Time - Clocks Generator.mp4
29.19 MB
~Get Your Files Here !/4. Verilog Module/2. Action time - Do your first testbench.mp4
29.15 MB
~Get Your Files Here !/7. Verilog Combinational Design/21. Action Time - demux_4x_nbit.mp4
29.11 MB
~Get Your Files Here !/7. Verilog Combinational Design/13. Action Time - 4to16 binary Decoder.mp4
28.74 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/7. Action Time - Nbit Comparator Function.mp4
28.22 MB
~Get Your Files Here !/11. Verilog State Machines/7. Verilog Mealy FSM Template.mp4
28.15 MB
~Get Your Files Here !/8. Verilog Sequential Design/6. Basics of edge-triggered logic.mp4
27.91 MB
~Get Your Files Here !/10. Verilog Memory Design/1. Basics of Semiconductor Memory.mp4
26.82 MB
~Get Your Files Here !/8. Verilog Sequential Design/11. Action Time - Shift_Reg_PIPO.mp4
25.82 MB
~Get Your Files Here !/12. Verilog Design Examples/4. Basics of Data Ecryption.mp4
25.62 MB
~Get Your Files Here !/8. Verilog Sequential Design/1. Sequential Logic Basics.mp4
25.44 MB
~Get Your Files Here !/7. Verilog Combinational Design/22. Master the Seven Segment Display Decoder.mp4
25.34 MB
~Get Your Files Here !/10. Verilog Memory Design/3. Action Time - Single Port Sync Read SRAM.mp4
24.78 MB
~Get Your Files Here !/8. Verilog Sequential Design/19. Action Time - Nbit Counter.mp4
23.44 MB
~Get Your Files Here !/7. Verilog Combinational Design/14. Action Time - 8to3 Encoder.mp4
23.36 MB
~Get Your Files Here !/12. Verilog Design Examples/1. Discover the First In First Out (FIFO) circuit.mp4
22.84 MB
~Get Your Files Here !/8. Verilog Sequential Design/23. Action Time - Clock Divider Nbit.mp4
22.72 MB
~Get Your Files Here !/7. Verilog Combinational Design/19. Action Time - mux_4x_nbit.mp4
22.68 MB
~Get Your Files Here !/7. Verilog Combinational Design/9. Action Time - Nbit Comparator.mp4
22.6 MB
~Get Your Files Here !/7. Verilog Combinational Design/11. Action Time - Nbit Decoder.mp4
22.5 MB
~Get Your Files Here !/3. Verilog Data Types and Operators/8. Action time - Vectors.mp4
22.47 MB
~Get Your Files Here !/5. Verilog Design Styles/3. Action Time - half adder structural.mp4
22.46 MB